It can be appreciated that several trends presently exist in the electronics industry. Devices are continually getting smaller, faster and requiring less power, while simultaneously being able to support and perform a greater number of increasingly complex and sophisticated functions. One reason for these trends is an ever increasing demand for small, portable and multifunctional electronic devices. For example, cellular phones, personal computing devices, and personal sound systems are devices which are in great demand in the consumer market. These devices rely on one or more small batteries as a power source while providing increased computational speed and storage capacity to store and process data, such as digital audio, digital video, contact information, database data and the like.
Accordingly, there is a continuing trend in the semiconductor industry to manufacture integrated circuits (ICs) with higher device densities. To achieve such high densities, there has been and continues to be efforts toward scaling down dimensions (e.g., at submicron levels) on semiconductor wafers. To accomplish such high densities, smaller feature sizes, smaller separations between features and layers, and/or more precise feature shapes are required, such as metal interconnects or leads, for example. The scaling-down of integrated circuit dimensions can facilitate faster circuit performance and/or switching speeds, and can lead to higher effective yield in IC fabrication processes by providing or ‘packing’ more circuits on a semiconductor die and/or more die per semiconductor wafer, for example.
It will be appreciated that processes for manufacturing integrated circuits comprise hundreds of steps, during which many copies of an integrated circuit can be formed on a single wafer. Generally, such processes involve creating several layers on and in a substrate that ultimately form a complete integrated circuit. This layering process can create electrically active regions in and on the semiconductor wafer surface. In metal-oxide-semiconductor (MOS) transistors, for example, a gate structure is created, which can be energized to establish an electric field within a semiconductor channel, by which current is enabled to flow between a source region and a drain region within the transistor. The source and drain regions facilitate this conductance by virtue of containing a majority of hole (p type) or electron (n type) carriers. The regions are typically formed by adding dopants to targeted areas on either side of the channel region in a semiconductor substrate.
Gate structures in MOS transistors generally include a gate dielectric and a contact or gate electrode. The gate contact generally includes an electrically conductive material, such as metal or doped polysilicon and is formed over the gate dielectric, which is itself formed over the channel region. The gate dielectric is an insulator material, the basic purpose of which is to prevent large ‘leakage’ currents from flowing from the conductive gate electrode into the conductive channel region when a voltage is applied to the gate contact, while allowing an applied gate voltage to set up an electric field within the channel region in a controllable manner.
It can thus be appreciated that one way to increase packing densities is to decrease the thickness of transistor gate dielectrics to shrink the overall dimensions of transistors, where a very large number of transistors are commonly used in IC's and electronic devices. However, making gate dielectrics thinner can have undesirable results, particularly where SiO2 is used. For example, one shortcoming of a thin SiO2 gate dielectric is increased gate leakage currents due to tunneling of charge carriers through the oxide. Also, a thin SiO2 gate dielectric layer provides a poor diffusion barrier to dopants. This may, for example, allow a subsequently applied dopant (e.g., boron) to penetrate into and contaminate the underlying channel region.
Consequently, recent efforts at device scaling have focused on alternative dielectric materials that are thicker than silicon dioxide (to minimize leakage through the gate dielectric) while exhibiting the same field effect performance. These materials are often referred to as high-k materials because their dielectric constants are greater than that of SiO2 (which is about 3.9). The relative performance of such high-k materials is often expressed as equivalent oxide thickness (EOT) because, while the alternative layer may be thicker, it still provides the equivalent electrical effect of a much thinner layer of SiO2. Accordingly, high-k dielectric materials can be utilized to form gate dielectrics, and the high-k materials facilitate a reduction in device dimensions while maintaining a consistency of desired device performance.
It can thus be appreciated that techniques for uniformly and controllably forming dielectric materials that have desired physical thicknesses while also possessing desired ‘electrical thicknesses’ or equivalent oxide thicknesses that facilitate device scaling while mitigating adverse effects associated with thin gate dielectrics (e.g., leakage currents) are in demand.